# NEORV32 RTL fuel-cost characterization — 2026-08-27

## Status and scope

Company-authored simulator characterization. This record reports observed
opcode-class costs in the no-cache NEORV32 register-transfer model under GHDL.
It is not physical-hardware evidence, WCET, timing sign-off, certification
evidence, or a complete control-loop budget.

The run retained its source hashes, generated RV32 binary, build log, simulator
transcript, tool versions, simulator configuration, raw counter values and
derivation in
`evidence/simulation/2026-08-27-neorv32-rtl-fuel-costs-02/manifest.json`.
The repository was dirty and that state is recorded verbatim in the manifest.

## Method

The harness measured 128- and 256-dispatch jump baselines to separate fixed
invocation overhead from marginal dispatch cost. Each opcode row then alternated
128 target operations with 128 measured jumps. The provisional credit table
uses the largest observation in each class, adds a 25% engineering margin and
rounds upward to 16 cycles.

| Charge | Provisional credits |
|---|---:|
| Fixed invocation overhead | 416 |
| ALU except multiply | 368 |
| Multiply | 352 |
| Load byte / half / word | 336 / 368 / 432 |
| Store byte / half / word | 320 / 368 / 400 |
| Branch or jump | 448 |
| Capability 0 / 1 / 2 harness stubs | 480 / 464 / 480 |
| Exit | 448 |
| Invalid path | 480 |

The interpreter uses these values as the versioned
`PROVISIONAL_NEORV32_RTL_V1` cost model. Step fuel still separately limits the
number of dispatched instructions. Timing credits are reserved before an
instruction executes, so an instruction that cannot be fully funded does not
run or enter a capability implementation.

## Operational status

The table characterizes one no-cache compiler and simulator configuration, with harness stubs for the three capability rows. One-tick operational admission follows once the deployed capability paths have frozen bounds.